This invention relates generally to semiconductor integrated circuit packaging and more particularly, it relates to an improved stacking scheme for micro-BGA (ball grid array) packages so as to provide a high density integrated circuit package.
In view of the rapid advancement made in the area of integrated circuit microprocessors, there have been developed a number of complex systems which utilize a variety of integrated circuit memory devices such as DRAMs and FLASH ROMs. As a result of the improved methods for miniaturization of integrated circuits containing millions of circuit elements on a single chip, there has arisen a need for enhanced packaging technology for the integrated circuits so as to package them in a relatively small amount of space. Heretofore, there are known in the prior art of various methods and apparatus for achieving high density integrated circuit packages.
As is generally known to those in the package and interconnection industry, there exists a high level of interest in the area of ball grid array (BGA) package and assembly technology. In this field of BGA technology, there are included plastic ball grid array (PBGA) packages, multilayer ceramic ball grid array (CBGA) packages, tape automated bonding (TAB) BGA packages, and ball grid array-like packages. The ball grid array-like packages are variations of the BGA theme and consist of SLICC, mini-BGA, and TCC. The TCC (Tessera Compliant Chip) is a chip array package developed by Tessera, Inc. of Elmsford, N.Y., and is also referred to as a micro-BGA.
In U.S. Pat. No. 5,258,330 to I. Y. Khandros and T. H. DiStefano issued on Nov. 2, 1993, and entitled "Semiconductor Chip Assemblies With Fan-In Leads," there is disclosed a semiconductor packaging technique utilizing a flexible circuit connected to the surface of the chip to provide the medium for routing the I/O contact pads of the chip into an array of bumps. FIG. 1 of the drawings of the instant patent application shows a prior art semiconductor chip package which is similar to the one in the '330 patent.
As can be seen from FIG. 1, a sheet-like dielectric interposer 36 is assembled to the semiconductor chip 20. The interposer 36 includes a flexible layer 38 and a compliant layer 40. A plurality of central terminals 48 are distributed over the surface 44 of the flexible layer 38 at substantial even spaces so as to define an "area array." The dimensions of the interposer 36 in the plane of the surface 44 are smaller than the corresponding dimensions of the chip 20 in the plane of its surface 22. As a result, the edges of the interposer are disposed inwardly of the rows of peripheral contacts 30 on the chip 20. Fine, flexible bonding wires 56 are applied in a wire bonding operation so as to connect electrically the peripheral contacts 30 on the chip 20 to the central terminals 48 via bonding terminals 52 and partial leads. Then, the chip 20, interposer 36 and bonding wires 56 are encapsulated in a conventional process so as to provide a durable assembly which can be easily handled.
Next, the chip and interposer subassembly is juxtaposed with a substrate 66 having electrical contact pads 68 formed thereon. The subassembly is placed onto the substrate so that each of the central terminals 48 faces toward and are aligned with corresponding electrical contact pads 68 on the substrate 66. Masses of an electrically conductive bonding material 70 such as solder or an electrically conductive adhesive is disposed between the central terminals 48 and the contact pads 68 of the substrate. The masses are caused to flow and to bond with the central terminals and the contact pads so as to form mechanical and electrical connections therebetween.
Since each of the peripheral contacts 30 on the chip 20 is connected to one of the central terminals 48 on the interposer 36 and since each of the central terminals 48 is further connected to one of the contact pads 68 on the substrate 66, then each peripheral contact 30 will be connected electrically to one of the contact pads 68. Further, the contact pads on the substrate can also be connected to other circuit elements through conventional connections when the substrate is a printed circuit board containing various electrical components besides the chip 20.
In order to provide a quick and cost-effective way to securely bind together a stack of individual integrated circuits, the '330 patent also disclosed a circuit assembly which includes a plurality of chip assemblies so as to form a larger multi-chip circuit assembly. FIG. 2 of the drawings of the instant patent application shows a prior art multi-chip circuit assembly which is similar to the one in the '330 patent. As shown in FIG. 2, a plurality of chip assemblies, each consisting of a chip 620, an interposer 636 and a sheet-like backing element 660, are arranged in a stack one atop the other, with the backing element 660 of each chip assembly overlying the interposer 636 of the next lower chip assembly other than the bottommost chip assembly.
It can be seen that in each chip assembly the interposer 636 overlies a central region of the chip 620 and has its central terminals 648 connected to the peripheral contact 630 of the chip by leads 650. The leads 650 have outer extensions 654 extending outwardly beyond the peripheral contact 630 and beyond the edges of the chip. The backing element 660 also extends outwardly beyond the edges of the chip and has outside terminals 666 dispose outboard of the chip edges on its top surface 662. The outward extension 654 of the leads 650 from the interposer 636 are connected to outside terminals 666 of the backing element and are secured thereto. The outside terminals 666 are electrically connected to inside terminals 668 disposed on the bottom surface 664 of the backing element. The inside terminals 668 are disposed in the central region of the backing element and have a pattern similar to the pattern of the central terminals 648 on the interposer 636.
The inside terminals 668 on the backing element of each chip assembly are aligned with the central terminals 648 on the interposer 636 of the immediate subjacent (next lower) chip assembly. Thus, these aligned terminals are mechanically and electrically connected to one another by masses of electrically conductive bonding materials 670 such as solder or electrically conductive adhesive. In this manner, the leads and contacts of the various chip assemblies are electrically connected to one another, thereby connecting the chips to one another. Moreover, the multi-chip circuit assembly can be further connected to a larger substrate by either bonding the central terminals 648 on the interposer 636 of the topmost chip assembly to a substrate or bonding the inside terminals 668 on the lowermost chip assembly to a substrate.
The inventor of the present invention has developed a way to easily modify the micro-BGA package of the prior art of FIG. 1 in order to facilitate stacking of the same without the need of the backing element 660 for each chip assembly. The unique stacking scheme of the present invention has particular applications for use with integrated circuit memory chips such as flash memory chips so as to achieve a high density package. The modified micro-BGA package can be stacked in a relatively small amount of area on a printed circuit board. Further, there is provided a unique signal line routing scheme to each of the layers of the stacked package.